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LZRW1 Compressor Core :: Overview

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Details

Name: lzrw1-compressor-core
Created: Apr 5, 2013
Updated: Dec 19, 2013
SVN Updated: Apr 7, 2013
SVN: Browse
Latest version: download
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Other project properties

Category: Arithmetic core
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Description

This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed data) at the expense of an somewhat lower compression ratio. One byte of uncompressed data can be processed at every second clock
cycle. A software decoder (decompressor) written in java is included.
The core is fully pipelined to allow high clock speeds. 66MHz can easily be achieved on a Spartan6
FPGA. This results in a maximum compression throughput of almost 32MBytes/sec.
It uses a Wishbone compliant slave interfaces to receive uncompressed data and configuration information. A second Wishbone (master) interface is used by the included DMA unit to directly transfer the compressed data to RAM or another Wishbone slave.
The project includes a file based test bench which compresses externally generated input files. The compressed file can be verified with an included java tool. Both the VHDL and java code have been tested with an Spartan6 FPGA and several 100MB of hardware generated random data.
The core occupies ~500 Spartan6 slices using 1605 FF/LUT pairs of which 44% are fully used.

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