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M16C5x :: Overview

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Name: m16c5x
Created: Nov 1, 2013
Updated: Nov 10, 2014
SVN Updated: Dec 6, 2013
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Latest version: download
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Other project properties

Category: System on Chip
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This project demonstrates the use of the P16C5x soft-processor core, found elsewhere on opencores.org, in a system-on-chip. The project targets a small FPGA, the Xilinx XC3S50A-4VQ100I. The project integrates the P16C5x PIC-compatible processor core an SPI Master module, SPIxIF, a Synchronous Serial Peripheral (SSP) slave module, SSP_Slv, an SSP UART, SSP_UART, and an inferred 4096 x 12 Block RAM program memory. (The SPIxIF, SSP_Slv, and SSP_UART modules are all modules that can be found on opencores.org.)

The P16C5x module is a PIC-compatible processor core that supports the 12-bit base architecture of the Microchip PIC16 product line. It extends the base architecture by supporting an additional address line into program memory. The base architecture does not implement the PA[2] program bank register in the STATUS register. The P16C5x module implements that bit, and adds an additional bit to the two-level stack so that a complete 4096 x 12 program space is available.

For compatibility with readily available PIC-compatible tools from Microchip, third-party vendors, and open-source suppliers, the P16C5x core has been parameterized such that the core's reset vector is set to be compatible with the corresponding vector of the PIC16C57/PIC16C59 microcomputer. The internal register/RAM memory map of P16C5x core has been set to be compatible with that of the PIC16C57 microcomputer: (1) I/O ports A, B, C are implemented; and (2) internal RAM is set for 72 bytes. (It is possible to increase the size of internal memory to support the banked switched memory of the PIC16C59, but the size of the FIFOs used for the UART may have to be changed to support the additional processor core RAM in the small FPGA chosen as the target for this project. Changing the FPGA to an XC3S200A-4VQ100I is possible, and that choice would allow the increase of the processor memory, and enable the use of Block RAMs for the UART FIFOs, and adding a second SSP_UART module to the M16C5X soft-microcomputer.)

Unlike a Microchip PIC16C57/PIC16C59 microcomputer, the I/O ports are not built into the M16C5x's P16C5x soft-core processor module. Instead, the P16C5x soft-core provides a parallel data bus with one-hot control signals for writing the three TRIS write-only registers and the three output data registers and reading the three input data registers. This allows the core's integrator the flexibility to create custom peripherals which are tightly integrated with the processor core in a manner that reduces the number of instructions needed to access the custom peripherals.

In the M16C5x, the SPI master interface module is integrated into the core using the TRIS C register as a write-only register. The SPI transmit and receive data registers are mapped to the Port C data output and data input registers, respectively. Furthermore, to take advantage of the capability of the SPIxIF module to operate with FIFOs connected, two 16x8 distributed RAM FIFOs are attached to the SPIxIF as the transmit and receive data ports. This allows the P16C5x processor core the opportunity to process other (beyond the scope of the demonstration) I/O or perform other computational functions while an SPI transaction is automatically fulfilled by the SPI master peripheral.

Beyond the testing performed with the simulator and various test benches, the M16C5x has been tested in a working board using the XC3S50A-4VQ100I FPGA. A simple test program was written using MPLAB (8.91) that simply converts lower case ASCII alpha characters into upper case characters, and vice versa. After configuring the SPI master and the SSP UART, it simply polls the UART, transforms the data, and writes it back to the UART. Even with all of this activity on the internal SPI bus, the M16C5x is able to process data at rates to 921.6 kbaud without errors or dropouts.

In the target FPGA, the smallest and lowest speed grade part in the Spartan 3A FPGA family, the M16C5x easily reports post synthesis speeds in excess of 57 MHz, and maps, places, and routes (with only simple period constraints) with reported and verified post-PAR performance better than 60 MHz. Since the core is a single cycle core, this is a substantial improvement over the capabilities of the equivalent Microchip products which are 5 MHz (effective instruction rate) devices.

A final component of the M16C5x project is the demonstration of the use of the Xilinx tool, Data2Mem, that allows specially formatted ASCII hexadecimal files to be written into the block RAMs of the device during the generation of the configuration images, i.e. directly inserted by BitGen. This allows a third party developer to write/modify the contents of the M16C5x program memories without requiring the resulting data to be loaded into the Block RAMs through re-synthesis and MAP/PAR operations. The resulting improvement in the turn around time for non-RTL modifications, i.e. firmware-only mods, is dramatic and far less error prone.

The TCL script included in the RTL source directory allows the integrator of this core to take advantage of this capability. (This capability is likely available from any FPGA vendor supporting soft-core processors. It is expected that Altera (NIOS-II) and Lattice (Mico-32) toolsets provide the same type of capability, but no verification has been performed to verify that these toolsets support this capability in their base (free) configurations.) The project provides a Block Memory Map (BMM) file, sets the mapper and the configuration bitstream generator (BitGen) to support use the BMM file. The project also provides a Windows executable (and its source code) for a simple filter/console program that converts Microchip MPLAB Intel Hex output files into Data2Mem-compatible MEM files.

Tool Set Compatibility

This core has been used with MPLAB and the CCS C compiler tools. A utility for converting from Intel Hex to Xilinx MEM files has been provided as part of this SoC project.

Synthesis/PAR Results

The data provided in this section represents the synthesis/PAR results of building the project for a XC3S50A-4VQ100I FPGA to achieve best performance. Thus, synthesis is performed with speed as its primary objective; resource sharing is used, but register balancing (forward and backward) is allowed. Mapping is performed with an area objective to compress the resulting image as much as possible. Simple timing constraints are applied for the three internal clock domains, with the primary objective being to achieve a minimum operating speed of 60 MHz for the P16C5x core, 66.667 MHz operation for the SPI Master (internal SPI bus), and 100 MHz for the SSP UART. The UART, although capable of operating at higher speeds, is fed a 29.4912 MHz reference clock. Module Level Utilization

Module Level UtilizationSun Nov 3 07:42:40 2013



ModulePartitionSlicesSlice RegLUTsLUTRAMBRAMMULT18X18BUFGDCM
[-] M16C5x/
166/110324/60473/12650/2113/30/01/40/1
  [-] CPU
231/387116/202306/48840/400/00/00/00/0
       ALU
78/7813/13112/1120/00/00/00/00/0
       IDEC
78/7873/7370/700/00/00/00/00/0
  [-] ClkGen
10/2011/245/81/10/00/01/30/1
       ClkGen
4/44/41/10/00/00/02/21/1
       FE1
4/46/61/10/00/00/00/00/0
       FE2
2/23/31/10/00/00/00/00/0
  [-] SPI
5/908/750/1350/340/00/00/00/0
       MSTR
43/4339/3967/670/00/00/00/00/0
       RF
21/2114/1433/3316/160/00/00/00/0
       TF
21/2114/1435/3518/180/00/00/00/0
  [-] UART
0/4400/2790/5610/1360/00/00/00/0
       SSP_Slv
50/5037/3728/280/00/00/00/00/0
       [-] UART
138/39081/242193/5330/1360/00/00/00/0
         BRG
15/1513/1326/260/00/00/00/00/0
         [-] INT
7/284/255/110/00/00/00/00/0
           FE1
4/43/31/10/00/00/00/00/0
           FE2
2/23/31/10/00/00/00/00/0
           RE1
4/44/41/10/00/00/00/00/0
           RE2
4/44/41/10/00/00/00/00/0
           RE3
2/23/31/10/00/00/00/00/0
           RE4
5/54/41/10/00/00/00/00/0
         RCV
35/3526/2656/560/00/00/00/00/0
         RED1
4/44/42/20/00/00/00/00/0
         RED2
3/34/42/20/00/00/00/00/0
         RED3
4/44/42/20/00/00/00/00/0
         RED4
4/44/42/20/00/00/00/00/0
         RED5
5/54/42/20/00/00/00/00/0
         RF1
55/5520/2093/9372/720/00/00/00/0
         TF1
51/5120/2085/8564/640/00/00/00/0
         TMR
20/2017/1726/260/00/00/00/00/0
         XMT
28/2820/2033/330/00/00/00/00/0



Timing Constraints
Timing ConstraintsSun Nov 3 07:41:40 2013




MetConstraintCheckWorst Case SlackBest Case AchievableTiming ErrorsTiming Score
YesTS_Clk = PERIOD TIMEGRP "Clk" 16.666 ns HIGH 50%SETUP HOLD0.039ns 0.834ns16.627ns0 00 0
YesTS_SPI_SCK = PERIOD TIMEGRP "SPI_SCK" 15 ns HIGH 50%SETUP HOLD0.337ns 1.064ns14.326ns0 00 0
YesTS_Clk_UART = PERIOD TIMEGRP "Clk_UART" 10 ns HIGH 50%SETUP HOLD1.318ns 0.785ns8.682ns0 00 0



Xilinx Design Summary
M16C5x Project Status (07/05/2013 - 18:41:59)
Project File: M16C5x.ise Current State: Programming File Generated
Module Name: M16C5x
  • Errors:
 
Target Device: xc3s50a-4vq100
  • Warnings:
 
Product Version: ISE 10.1.03 - Foundation
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
 
M16C5x Partition Summary [+]
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 604 1,408 42%  
Number of 4 input LUTs 1,217 1,408 86%  
Logic Distribution     
Number of occupied Slices 692 704 98%  
    Number of Slices containing only related logic 692 692 100%  
    Number of Slices containing unrelated logic 0 692 0%  
Total Number of 4 input LUTs 1,265 1,408 89%  
    Number used as logic 1,006      
    Number used as a route-thru 48      
    Number used as 16x1 RAMs 8      
    Number used for Dual Port RAMs 170      
    Number used for 32x1 RAMs 32      
    Number used as Shift registers 1      
Number of bonded IOBs
Number of bonded 20 68 29%  
    IOB Flip Flops 5      
Number of BUFGMUXs 4 24 16%  
Number of DCMs 1 2 50%  
Number of RAMB16BWEs 3 3 100%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [+]

Date Generated: 11/03/2013 - 07:36:08 Number of BUFGMUXs 4 24 16%   Number of DCMs 1 2 50%   Number of RAMB16BWEs 3 3 100%    
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [+]

Date Generated: 11/02/2013 - 13:56:37

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