OpenCores

M32632 32-bit Processor :: Overview

Project maintainers

Details

Name: m32632
Created: Jun 24, 2015
Updated: May 5, 2016
SVN Updated: Mar 8, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: LGPL

Description

M32632 is an implementation of the Series 32000 architecture of National Semiconductor.
This 32-bit architecture was popular in the 1980's and began to disappear in the beginning
of the 1990's. The first microprocessor was the NS32016. The third generation CPU was
the NS32532. This processor is the basis of M32632. In addition M32632 implements the
functionality of the NS32381 floating point unit.

Current status

  • 27 June 2015 - initial version 1.0 .
  • 7 October 2015 - 5 verilog files modified due to a bug. Their version number is now 1.1 .
  • 7 November 2015 - verilog file I_PFAD.v modified due to a bug. Its version number is now 1.1 .
  • 21 January 2016 - verilog files DECODER.v and STEUER_MISC.v modified due to a bug. Their version number is now 1.1 .
  • 4 February 2016 - verilog file I_PFAD.v modified due to a bug. Its version number is now 1.2 .
  • 8 March 2016 - verilog file ADDR_UNIT.v modified due to a bug. Its version number is now 1.2 .

Features

The M32632 has the following features:

  • simple instructions are executed in one clock cycle,
  • 8 kByte instruction cache,
  • 8 kByte write-through data cache,
  • one direct mapped TLB of 256 entries for each cache,
  • basic floating-point instructions for 32-bit and 64-bit data types,
  • coprocessor interface for custom instructions,
  • small size of 15400 LEs,
  • 35 MHz clock speed in Altera Cyclone IV FPGA.

Performance

The performance of M32632 at 35 MHz has been measured on a system running NetBSD 1.5.3 with the Dhrystone 1 Benchmark compiled with gcc. The source code of Dhrystone was taken from the link at the processor project ao486. The following numbers were achieved:

  • 10.69 VAX Mips non-optimized
  • 16.99 VAX Mips optimized with -O3

The numbers for Dhrystone 2.1 are slightly less. Please note the different optimization level.

  • 10.56 VAX Mips non-optimized
  • 16.12 VAX Mips optimized with -O2

The Linpack Benchmark is a well known program to measure the floating point performance of a computer. The original program was written in Fortran. It can be found here: http://www.top500.org/resources/frequently-asked-questions/ . Compiled with gcc with optimization level -O3 the M32632 achieves

  • 2.163 double precision Mflop/s

Acorn 32016 Second Processor for BBC micro

The actual version of M32632 can't be used as the processor for the Acorn 32016 Second Processor. The version 2 of M32632 can be used. Release of version 2 is planned for later this year. In case that you will start earlier with an FPGA implementation of 32016 Second Processor please contact the maintainer.

© copyright 1999-2016 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.