M32632 32-bit Processor :: Overview

Project maintainers


Name: m32632
Created: Jun 24, 2015
Updated: Aug 14, 2016
SVN Updated: Aug 15, 2016
SVN: Browse
Latest version: download
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Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: LGPL


M32632 is an implementation of the Series 32000 architecture of National Semiconductor.
This 32-bit architecture was popular in the 1980's and began to disappear in the beginning
of the 1990's. The first microprocessor was the NS32016. The third generation CPU was
the NS32532. This processor is the basis of M32632. In addition M32632 implements the
functionality of the NS32381 floating point unit.

Current status

  • 27 June 2015 - initial version 1.0 .
  • 14 August 2016 - release of version 2.0 .


The M32632 has the following features:

  • simple instructions are executed in one clock cycle,
  • 8 kByte instruction cache,
  • 8 kByte write-through data cache,
  • one direct mapped TLB of 256 entries for each cache,
  • basic floating-point instructions for 32-bit and 64-bit data types,
  • coprocessor interface for custom instructions,
  • small size of 15400 LEs,
  • 50 MHz clock speed in Altera Cyclone IV FPGA.


The performance of M32632 at 50 MHz has been measured on a system running NetBSD 1.5.3 with the Dhrystone 2.1 Benchmark compiled with gcc. The source code of Dhrystone was taken from the link at the processor project ao486. The number is:

  • 38601 which is equal to 21.97 VAX Mips optimized with -O2

The Linpack Benchmark is a well known program to measure the floating point performance of a computer. The original program was written in Fortran. It can be found here: . Compiled with gcc with optimization level -O3 the M32632 achieves

  • 3.02 double precision Mflop/s

DE0-Nano Demonstration System

For the DE0-Nano board using an Altera Cyclone IV E FPGA is a demonstration system available. The data for it is contained in the directory trunk/DE0-Nano. The M32632 running at 50 MHz is connected to a 32 MB SDRAM running at 100 MHz. The program for the processor flashes the LEDs on the board. Changing the configuration is easily possible. The source code for the SDRAM controller is included.

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