OpenCores

McAdam's RISC Computer Architecture :: Overview

Project maintainers

Details

Name: marca
Created: Feb 1, 2007
Updated: Feb 2, 2007
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: GPL

Description

McAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.

Features

- 16 16-bit registers
- Harvard architecture
- all memories on-chip
- 16KB instruction ROM
- 8KB data RAM
- 256 byte data ROM
- load/store instruction set architecture
- 75 instructions
- 16 interrupt vectors
- 4-stage pipeline

Status

- running on an Altera Cyclone FPGA

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.