ODESS Multicore Project :: Overview

Project maintainers


Name: odess_multicore_project
Created: Aug 10, 2017
Updated: Sep 13, 2017
SVN: No files checked in

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL

Main features.

1. Up to 255 processor cores may be used to make a two-dimensional multiprocessor network matrix with size 16x16.
2. Hardware support of multiple process execution in time division mode for each processor core.
3. Hardware data stream technology allows to transfer data between general purpose registers of different cores immediately. Also, hardware data stream technology can be used for fast data transfer from one process to another, which executed on a same core. Each processor core can create up to 255 incoming data streams.
4. All control communications between executed processes based on a message transfer mechanism. Each process has its own message queue. Two message queues – system messages queue and regular messages queue. A message descriptor and a message parameter are placed in the message queue. The transmission of a message is initiated by a single machine instruction. Messages can be transferred between processes running on the same core and between processes running on different cores of the multiprocessor network.
5. A built-in memory management system that allows executable processes to allocate memory blocks for storing data and free unnecessary ones using a single machine instruction.
6. The protection of data objects located in memory is based on a four-level data and code privilege scheme, as well as 16-bit group identifiers.
7. Simultaneous execution of up to 8 instructions per clock in peak and up to 4 instructions per clock in continuous mode.
8. The sequence control system sends instructions for execution, depending on the readiness of their source operands and the result receiver. Instructions may not be executed in the order in which they are written in the program.
9. Support for single (32-bit), double (64-bit) and quadruple (128-bit) floating point data formats. Standard IEEE-754 used.
10. 16-bit instruction format, giving a compact code. The exception is 3 instructions for formatting data. They have a length of 32 bits.
11. 16 128-bit general-purpose registers, 16 32-bit flags registers tied to each general-purpose register, 16 37-bit address registers used to address memory. A set of system control registers is allocated in the memory space.
12. 64-bit internal data bus architecture, 45-bit physical address of local memory for each core.
13. For data and code addressing, a three-part logical address is used that contains an 8-bit processor / core number, a 24-bit object selector, and a 37-bit offset within the object. The object selector addresses a 32-byte object descriptor that specifies the location of the object in physical memory, its size, type, and rules for accessing the object.

PDF Documentation

Processor architecture:!537960075747
Internal registers:!833361470041
Instruction set reference:!201289397137
Address translation and memory protection:!095098926468
Multiple process execution and message exchange system:!660901703252
Multiprocessor structure and packet formats:!602522820153
System error processing:!425804019409
Data streams:!662247105405


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