OPB PSRAM Controller :: Overview

Overview

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Project maintainers

Koethe, Daniel

Details

Name: opb_psram_controller
Created: Feb 9, 2008
Updated: Feb 16, 2008
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Memory core
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License: GPL

Description

The OPB PSRAM-Controller connect a Pseudo-Staic-RAM, also named CellularRAM™ to the OPB-Bus.

Features

Design
- max. 80 Mhz Memory Clock for a Spartan-3 1500 FPGA
- synchronous design, no DCM/DLL needed
Performance with micron MT45W8MW16BGX-701
- 32-Bit Write: 3 Clock cycles
- 32-Bit Read: 8 Clock cycles

Status

- Design Phase done
- Simulation Tests done
- Real-World Tests done