OpenFIRE :: Overview
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The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze. Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson. The OpenFire was developed by Stephen Craven specifically for configurable array research. As such, certain features of the MicroBlaze are not currently implemented. The OpenFire lacks interrupts, exceptions, debugging facilities, and Local Memory Bus and On-chip Peripheral Bus interfaces. These functions may be added in the future. The page of the author is: http://www.ccm.ece.vt.edu/~scraven/openfire.html
The version posted in opencores is an improved version of the Openfire I'm working on with the author permission and the goal is to have a functional SoC with a 32 bit RISC CPU and a set of peripherals ready to be used by several projects.
The initial target board / FPGA are the Spartan3 starter board with XC3S200. Althought I'm using plain verilog some borrowed peripherals (mainly from the Xilinx application notes) are Xilinx specific. In the near future vendor independent peripherals will be added.
- OpenFIRE CPU
- Features can be enabled/disabled with `defines
- ISA compatible with Microblaze
- FSL link
- Exceptions (invalid opcode and alignment)
- Special registers support (not completed)
- Memory interface
- Dissasembler for simulation of CPU with applications
- OpenFIRE SOC
- All parameters are configurable via `defines
- Peripherals selectables via `defines and mapped in memory
- VGA (640x480) : mapped into SRAM
- Up to 2 UART
- PROM loader (as FPGA PROM is not 100% full you can add programs and data at the end of the FPGA bitstream)
- board GPIO (7seg displays, switches and push buttons)
- External memory controller (SRAM)
- SPI / I2C
- OpenFIRE CPU
- ISA almost completed
- MSR bits (IE, BIP, EIP, etc..)
- Special register handling 50% (mfs, mts)
- Pending: div and barrel shift
- Memory access code rewritten in order to allow multicycle read/writes for INS/DATA ports
- Unaligned data read/write removed from cpu (moved to memory handler at soc level).
- OpenFIRE SOC
- Work in progress in several peripherals
- Boot monitor in 2Kbytes of FPGA BlockRAM with minimal monitor capabilities (dump/write/fill, etc..) and able to load/execute programs from UART(Motorola S records) or PROM (binary file)
- Port of FreeRTOS in progress (Microblaze port is not working due to different peripherals and minimal differences in MSR)
- Port of lwIP TCP/IP stack in progress (with slip interface at the moment)
- low level driver for uart input/output used by gnu libc (printf, etc..)
- vga library (display texts and limited drawing). work in progress.
- Microblaze toolchain:
- Source code / linux binary: http://www.petalogix.com/resources/downloads/mb-gcc
- Windows binary: http://www.xilant.com/downloads/mb_gnu_8_2.zip
- Microblaze uClinux: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
- Microblaze documentation: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=micro_blaze
Instructions to install/configure working testbench for Spartan3 Starter Kit:
Please note that all the helper utilities (bin2xx.c) are compiled only for Windows; you may need to recompile they if using linux.
1. Create an ISE project with all the verilog files (except openfire_template_bootram.v). Adjust openfire_define.v as needed.
2. Include constraint file: sp3_devboard.ucf
3. Make the monc program with Microblaze toolchain (cd sw/monc and make then a file monc.v will be generated). Include it in the project openfire_soc
3. Generate a bitstream for the openfire_soc.v module
4. Burn the bitstream to the FPGA prom.
5. Connect a serial port to SP3SK board (115200-n-8-1). Push "reset" (reset is pushbutton #4) a welcome and a prompt should appear.
Now you have the openfire cpu/soc with a set of peripherals and a monitor loaded in block ram.
6. Make the low level library (sw/lib then make)
7. Make FreeRTOS library (sw/freertos then make)
8. Make vga library (sw/vga then make) and the vga example (vga.srec)
Now you are ready to make programs and load them into SRAM. In order to load a program you can use load.bat to upload Motorola SREC dumps. Previously configure COM1 port (mode com1:115200,n,8,1). When the program is loaded you must connect with a terminal to SP3SK board and type "x 04000000"