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OpenFire Processor Core :: Overview

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Details

Name: openfire_core
Created: Aug 24, 2007
Updated: Dec 13, 2007
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
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Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info: FPGA proven
WishBone Compliant: No
License:

Description

The OpenFire Processor Core is an open-source, binary-compatible MicroBlaze clone written in Verilog. Binary-compatible means exactly that - a binary compiled for a MicroBlaze embedded system will run on an OpenFire that is placed in the same embedded system. The OpenFire was designed for use in SCMP (Single Chip, Multiple Processor) and ASIP (Application Specific Instruction-set Processor) research. The OpenFire has an advantage in these areas as the entire HDL source is available, creating ultimate flexibility.

The OpenFire Processor Core was written by Stephen Craven, a PhD student at Virginia Tech. It has been most recently upgraded by Alex Marschner, a Masters student at the same university. The OpenFire Processor Core is released under the MIT license.

Features

- binary compatibility with the Xilinx MicroBlaze
- full FSL (Fast Simplex Link) support
- 8 master ports (output)
- 8 slave ports (input)
- full OPB (On-chip Peripheral Bus) support
- Data-side OPB support allows access to Xilinx OPB peripherals.
- Instruction-side OPB support allows programs to run from off-chip memory.
- The latency of the LMB (Local Memory Bus) is removed by using a direct BRAM memory.
- The OpenFire can be used in the EDK, although programming is still done manually.
- 50MHz operation

Project Status

- 2007.12.12 OpenFire v0.6a is released

Future Work

- Add XMD debug support
- Add PLB support
- improve memory-mapping design
- move more #define values to module parameters (where appropriate)
- improve speed to 100MHz +
- improve integration with the Xilinx EDK
- allow software creation from within the EDK
- force the EDK to recognize the OpenFire as a processor

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