Global control
Table of content
1. Introduction
This section describes the global control, status and interrupt flag registers.
2. Registers
2.1 GFX_CTRL
Address: 0x00 |
Global control register |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
res. |
GPU_EN |
res. |
GFX_MODE |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
IE_GCMD_E |
IE_GCMD_D |
IE_GFIFO_O |
IE_GFIFO_D |
res. |
IE_RCDONE |
IE_RSTART |
IE_RDONE |
| • GPU_EN | : Enable Graphic Processing Unit
0 = GPU is disabled
1 = GPU is enabled |
| • GFX_MODE | : Graphic Mode Configuration (bit-per-pixel)
000 = 1 bit-per-pixel
001 = 2 bit-per-pixel
010 = 4 bit-per-pixel
011 = 8 bit-per-pixel
others = 16 bit-per-pixel |
| • IE_GCMD_E | : GPU command error interrupt enable bit
0 = disable GPUCMD error interrupt
1 = enable GPUCMD error interrupt |
| • IE_GCMD_D | : GPU command done interrupt enable bit
0 = disable GPUCMD done interrupt
1 = enable GPUCMD done interrupt |
| • IE_GFIFO_O | : GPU FIFO overflow interrupt enable bit
0 = disable GPUFIFO overflow interrupt
1 = enable GPUFIFO overflow interrupt |
| • IE_GFIFO_D | : GPU FIFO done interrupt enable bit
0 = disable GPUFIFO done interrupt
1 = enable GPUFIFO done interrupt |
| • IE_RCDONE | : Screen refresh counter done interrupt enable bit
0 = disable REFR counter done interrupt
1 = enable REFR counter done interrupt |
| • IE_RSTART | : Screen refresh start interrupt enable bit
0 = disable REFR start interrupt
1 = enable REFR start interrupt |
| • IE_RDONE | : Screen refresh done interrupt enable bit
0 = disable REFR done interrupt
1 = enable REFR done interrupt |
2.2 GFX_STATUS
Address: 0x08 |
Global status register |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
res. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
res. |
STA_GBUSY |
res. |
STA_GFIFO |
res. |
STA_RBUSY |
| • STA_GBUSY | : GPU busy status bit
0 = GPU is idle
1 = GPU is busy |
| • STA_GFIFO | : GPU FIFO status bit
0 = GPU FIFO is empty
1 = GPU FIFO is not empty |
| • STA_RBUSY | : Screen refresh busy status bit
0 = no screen refresh on going
1 = screen refresh currently on going |
2.3 GFX_IRQ
Address: 0x00 |
Global control register |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
res. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
IF_GCMD_E |
IF_GCMD_D |
IF_GFIFO_O |
IF_GFIFO_D |
res. |
IF_RCDONE |
IF_RSTART |
IF_RDONE |
| • IF_GCMD_E | : GPU command error interrupt flag bit
0 = no GPU command error was detected
1 = GPU command error detected (write '1' to clear) |
| • IF_GCMD_D | : GPU command done interrupt flag bit
0 = GPU is IDLE or busy
1 = GPU command execution completed (write '1' to clear) |
| • IF_GFIFO_O | : GPU FIFO overflow interrupt flag bit
0 = GPU FIFO didn't overflow
1 = GPU FIFO overflow detected (write '1' to clear) |
| • IF_GFIFO_D | : GPU FIFO done interrupt flag bit
0 = GPU FIFO's last word was not read
1 = Last GPU FIFO word was read (write '1' to clear) |
| • IF_RCDONE | : Screen refresh counter done interrupt flag bit (see here)
0 = screen refresh counter is either 0 or still running
1 = screen refresh counter reached 0 (write '1' to clear) |
| • IF_RSTART | : Screen refresh start interrupt flag bit
0 = no new screen refresh started
1 = a new screen refresh started (write '1' to clear) |
| • IF_RDONE | : Screen refresh done interrupt flag bit
0 = no screen refresh has completed
1 = screen refresh completed (write '1' to clear) |