OpenCores

Open JTAG project :: Overview

Project maintainers

Details

Name: openjtag-project
Created: Jun 1, 2010
Updated: Oct 22, 2010
SVN Updated: Jun 27, 2010
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Testing / Verification
Language: VHDL
Development status: Beta
Additional info: none
WishBone Compliant: No
License: LGPL

Description

The Open JTAG project has as objetive to give to the public domain a complete hardware and software JTAG project. Based on a simple hardware board, composed basically by a FT245 USB front end and an Altera EPM570 MAX II CPLD, this board is capable to output TCK signal at 24 MHZ using macro-instructions sent from the computer end.

It is not as others JTAG projects based on the PC parallel port: Open JTAG project uses the USB channel (still not at high speed) to communicate with the internal CPLD, sending macro-instruction as fastest as possible.

You can visit the official page of the project at http://www.openjtag.org/

© copyright 1999-2014 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.