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openVeriFLA - FPGA logic analyzer :: Overview

Project maintainers

Details

Name: openverifla
Created: Jul 31, 2007
Updated: Mar 3, 2008
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Library
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL

openVeriFLA - FPGA logic analyzer

openVeriFLA is an FPGA integrated logic analyzer.
It can be used for in-circuit debugging and verification
of the FPGA based applications.
The FPGA part is written in verilog. The PC part
is written in java and is platform independent.
Being simple and well documented, the openVeriFLA library
is well suited for didactical purposes and academic use.

For more information, please unzip the project archive
and read the reference manual.

Features

- on-the-fly capture, graphical display, testing automation

Status

- ready to use

IMAGE: verifla_keyboard_protocol_verification_50procent.jpg

FILE: verifla_keyboard_protocol_verification_50procent.jpg
DESCRIPTION: The FPGA capture of a keyboard controller signals

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