Documented Verilog UART :: Overview

Project maintainers


Name: osdvu
Created: Jun 28, 2010
Updated: Feb 29, 2016
SVN Updated: Jun 29, 2010
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Beta
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others


Open Source Documented Verilog UART


This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. All the open source UART modules I found were difficult to interface with, usually due to being more clever than I wanted them to be, and had poor documentation for their interfaces. They were also generally written in VHDL, which since I've never written VHDL made it a little difficult to read to work out the interfacing issues for myself. The frustration of finding such a simple component so hard to use prompted the decision to create my own, and document it for beginners like myself.

I hope that this module will be documented to a better standard than most I've come across. Please send me a message if you have trouble understanding it. Confusing documentation should be treated as much like a bug as a flaw in the code - please feel free to file one. Improvements are also welcome!

This is released under the MIT licence, which freely permits use in both open source and closed source / commercial projects.

What would I use this for?

A UART is a useful component for controlling asynchronous (without a separate clock line) serial buses. It can be used via a level converter to talk to the RS232 serial port of a computer. This is not, however, the only application. It can also be used in a circuit to communicate with peripherals, or over other types of cables (such at RS485 with a differential driver) to connect to other circuits over quite long distances.

I/O Standards, Compatability

This follows standard UART signalling methods with the following properties:

* Expects to send and receive data as 8 data bits, no parity bits.
* Default baud rate is 9600 with a 50MHz clock. This is configurable.
* Samples values roughly in the middle of each bit (may drift slightly).
* Sends and receives least significant bit first.
* Expects to receive at least 1 stop bit. Will not check for more, but won't fail if more are present either.
* Transmits 2 stop bits.
* Tested connecting over a computer serial port at standard rates up to 57600 baud.

Source Control

The source for this project is maintained using Git ( ). The latest source can be obtained by installing Git and running:

git clone git://

The source can be browsed online at:

The OpenCores SVN will be updated with each packaged release, but does not contain interim development.

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