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Documented Verilog UART :: News

News

Jul 30, 2010 Add advice on choosing speed.
Jun 29, 2010 Reduce tested frequency - getting some errors at >57600 baud.
Jun 29, 2010 Altered the interface to this slightly - the clock rate divider setting has changed to support high baud rates (tested up to 230400 baud). New formula in documentation.
Jun 29, 2010 Added files to SVN, removing alternate download
Jun 29, 2010 Fixing a bad grammatical
Jun 28, 2010 Added license terms to front page to make this as clear as possible.
Jun 28, 2010 Project setup
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