OpenCores

Parallel CRC Generator :: Bugtracker

Request(s)
Date Title Status Assigned to Submitted by
Jul 9, 2013 Synhronous clear input OPENED pela
Jul 9, 2013 Verilog comment characters in VHDL file OPENED pela
Bug(s)
Date Title Status Assigned to Submitted by
Jul 9, 2013 Incorrect checksum OPENED pela
Jun 7, 2011 Something going wrong OPENED RiZsho
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