PCIe SG DMA controller :: Overview
Other project properties
This package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6.
The design implements MAC, Physical (Xilinx Hard and Soft IP Cores) and Transaction Layer (Custom Core) of PCIe.
It holds 3 BAR’s, BAR, BAR and BAR, as its memory space. Registers are accessed via BAR, including the system registers, DMA channel registers and some other control and status registers. Block RAM are assigned to BAR. BAR contains the FIFO data ports, both write and read. FIFO control and status registers reside in BAR. All 3 applied BARs are accessible with PIO operation (PIO to the FIFO can only access 32 bits of the 64-bit bus). DMA can only target on BAR and BAR, 64-bit full bus.
The design was split into two projects: one for Virtex5 (in "Trunk" folder) and the other for Virtex6 (in "branches" folder).
It was fully tested on:
- AVNET Virtex5 PCIe Development Board
- Xilinx Virtex6 ML605 Development Board
Simulation is provided in Verilog HDL for both platforms.
The design is composed by some Xilinx IP Cores. Both the VHDL code and the CoreGen .xco file are provided. To change or upgrade them, a valid license for the cores from Xilinx Inc. should be available. The PCIe core is the 1.6 version in ISE12.3 and 1.7 versione in ISE 13.3. The old 1.3 version is also provided.
The DMA throughput depends on OS, machine, implementation and packet size:
On a Dell Precision T5500 with Linux Debian 2.6.32 64bit we measured:
- PCIe gen1.0 x4: write: up to 700 MB/s - read: up to 380 MB/s
- PCIe gen2.0 x1: write: up to 426 MB/s - read: up to 417 MB/s
- PCIe gen1.0 x4: write: up to 828 MB/s - read: up to 524 MB/s
Another Virtex5 board DMA performance test under Linux achieves
- PCIe Gen1 x4: write 790 MB/s; read 543 MB/s (FIFO) or 507 MB/s (BRAM).
Linux driver are avaible at: http://li5.ziti.uni-heidelberg.de/mprace/ (THX to Dr. Guillermo Marcus)