Pipelined fixed point elementary functions (div, sin, cos, exp, atan2, sqrt)
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Details
Name: pipelined_fixed_point_elementary_functions
Created: Dec 22, 2013
Updated: Jan 7, 2014
SVN Updated: Dec 31, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Dec 22, 2013
Updated: Jan 7, 2014
SVN Updated: Dec 31, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star3you like it: star it!
Other project properties
Category:DSP core
Language:Verilog
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Conveyored (result on every clock) elementary functions, implemented with CORDIC for demoscene project (http://www.youtube.comwatch?v=oh1_MzuFtdU). Number sizes in bits parametrized. Tested by eye, on DE2-115 board with VGA display.
Testing environments for DE2-115 and Marsohod II dev. boards included. DE2-115 testing environment may contain some board related code copyrited by Terasic or Altera.
Test projects for DE0 and DE0_nano dev. boards may be added on request.
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