Plasma - most MIPS I(TM) opcodes

Description

The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART, SRAM or DDR SDRAM controller, and Ethernet controller. The Plasma CPU executes all MIPS I(TM) user mode instructions except unaligned load and store operations (see "Avoiding Limitations" below).

This "clean room" CPU core is implemented in VHDL with either a two or three-stage pipeline. It is running at 25 MHz on a Xilinx FPGA and also verified on an Altera FPGA.

Success Stories

The Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server on a Xilinx FPGA.
     

Block diagram

IMAGE: cpu.gif

FILE: cpu.gif
DESCRIPTION:

Example Instruction

The CPU is implemented with a two or three stage pipeline with an additional optional stage for memory read and writes. (Using the three stage pipeline enables "pipeline.vhd" which delays some control signals into the next stage.) An ADD instruction would take the following steps:

Stage #0:

1. The "pc_next" entity passes the program counter (PC) to the "mem_ctrl" entity which fetches the opcode from memory.

Stage #1:

2. The memory returns the opcode.

Stage #2:

3. "Mem_ctrl" passes the opcode to the "control" entity.
4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
5. Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".

Stage #3 (part of stage #2 if using two stage pipeline):

6. Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
7. Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
8. Based on the c_source control signals, "bus_mux" multiplexes c_bus onto reg_dest.
9. Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.

Stage #4 (part of stage #3 if using two stage pipeline):

10. Read or write memory if needed.

Plasma Version 3 Features

The Plasma Version 3 core now contains a bidirectional serial port, interrupt controller, and hardware timer. Version 3.5 added a DDR SDRAM controller, Ethernet MAC, and Flash interface. There is C and assembly code for the Plasma Real-Time Operating System -- a fully preemptive RTOS supporting threads, semaphores, mutexes, message queues, timers, heaps, an interrupt manager, ANSI C library, single precision floating point library, TCP/IP protocol stack, and Web server.

List of Files

FILE	PURPOSE (Directory: vhdl)
code.txt	Input opcodes for the test bench -- test.axf "converted"
mlite_pack.vhd	Constants and Functions Package
tbench.vhd	Test Bench that uses plasma.vhd
plasma_if.vhd	Top level interface to Xilinx or Altera FPGA
plasma_3e.vhd	Top level interface to Xilinx Spartan-3E with DDR
-ddr_ctrl.vhd	DDR controller
-plasma.vhd	CPU core with RAM and UART
--cache.vhd	Optional 4KB cache
--ram.vhd	Internal RAM for Altera FPGA
--ram_xilinx.vhd	Internal RAM for Xilinx FPGA
--uart.vhd	UART (can pause CPU if needed)
--eth_dma.vhd	Ethernet MAC with DMA
--mlite_cpu.vhd	Top Level VHDL for CPU core
---alu.vhd	Arithmetic Logic Unit
---bus_mux.vhd	BUS Multiplex Unit
---control.vhd	Opcode Decoder
---mem_ctrl.vhd	Memory Controller
---mult.vhd	Multiplication and Division Unit
---pc_next.vhd	Program Counter Unit
---reg_bank.vhd	Register Bank for 32, 32-bit Registers
---shifter.vhd	Shifter Unit

FILE	PURPOSE (Directory: tools)
makefile	Makefile for the PC for creating "code.txt"
plasma.h	Plasma header file for register addresses
boot.asm	Initializes $gp and $sp, clears .bss
opcodes.asm	Tests all the MIPS I(tm) opcodes
convert.c	Converts test.axf to code.txt
ram_image.c	Creates Xilinx RAM file ram_image.vhd from ram_xilinx.vhd and code.txt
bootldr.c	Serial port boot loader that can download another program
etermip.c	Terminal program to download code and transfer Ethernet packets
mlite.c	Simulates the CPU in software
bintohex.c	Converts test.exe to code[0-3].hex for lpm_ram for Altera FPGA
test.c	Test program (opcodes) for the CPU core
pi.c	Calculates the first 16 digits of PI
count.c	Test program that counts using words
ddr_init.c	Initialize the DDR chip
cpu.gif	Block Diagram

FILE	PURPOSE (Directory: kernel)
makefile	Makefile for Plasma RTOS
rtos.h	Header file for Plasma RTOS
rtos.c	Plasma pre-emptive Real-Time Operating System
libc.c	ANSI C library subset
math.c	Single precision floating point library
uart.c	Serial port driver
rtos_test.c	Test the RTOS functions
tcpip.h	TCP/IP header file
tcpip.c	TCP/IP protocol stack
ethernet.c	Ethernet MAC
http.c	Web server
filesys.c	File system
flash.c	Flash access
netutil.c	FTP server/client and telnet server

Downloads

The Opencores Subversion web page can create the 130KB plasma_latest.tar.gz file containing all the latest code.

Tools

The MIPS(tm) GCC ELF compiler for Windows is available gccmips_elf.zip (2.4MB). The OpenCores server wouldn't let me save zip files so I had to rename it with an '.odt' extention. Rename the file from gccmips_elf.odt to gccmips_elf.zip before unzipping the files into the trunk\gccmips_elf directory. Add this directory to your executable PATH environment: set path=%PATH%;YOUR_DIR\trunk\gccmips_elf

If you use Windows and don't have a Microsoft C compiler for Windows, you will need pre-compiled versions of the tools (rename as tools.zip) which should be placed in the tools directory.

You may also need a Windows version of gmake. Rename the file gmake_zip.odt to gmake.zip before unzipping.

Supporting Documentation

See the tabs at the top for additional build instructions:

• The Plasma CPU instruction set
• Building the tools
• Additional Linux GNU MIPS tools
• Building the Plasma RTOS
• Building the Plasma TCP/IP stack

The implementation is based on information found in:

• "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
• "The Designer's Guide to VHDL" by Peter J. Ashenden

The MIPS I(TM) instruction set can be found by:

• Go to the MIPS Technologies, Inc. Web site http://www.mips.com/.
• Under the Products menu, click on Resource Library.
• Click on Product Materials in the submenu on the left.
• Click on MIPS Architecture from the next menu on the left.
• Finally, click on the link for "MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set (.pdf)".

Big/Little Endian

The CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.

Bus Interface

All signals are active high. Here are the signals for writing a character to address 0xffff when using a two stage pipeline:

   entity mlite_cpu is
      port(clk          : in std_logic;
        reset_in     : in std_logic;
        intr_in      : in std_logic;

        address_next : out std_logic_vector(31 downto 2); --for synch ram
        byte_we_next : out std_logic_vector(3 downto 0);

        address      : out std_logic_vector(31 downto 2);
        byte_we      : out std_logic_vector(3 downto 0);
        data_w       : out std_logic_vector(31 downto 0);
        data_r       : in std_logic_vector(31 downto 0);
        mem_pause    : in std_logic);
   end; --entity mlite_cpu

  Program:
  addr     value  opcode 
  =============================
    3c: 00000000  nop
    40: 34040041  li $a0,0x41
    44: 3405ffff  li $a1,0xffff
    48: a0a40000  sb $a0,0($a1)
    4c: 00000000  nop
    50: 00000000  nop

      intr_in                             mem_pause
  reset_in                               byte_we     Stages
     ns         address     data_w     data_r        40 44 48 4c 50
   3600  0  0  00000040   00000000   34040041  0  0   1  
   3700  0  0  00000044   00000000   3405FFFF  0  0   2  1  
   3800  0  0  00000048   00000000   A0A40000  0  0      2  1  
   3900  0  0  0000004C   41414141   00000000  0  0         2  1
   4000  0  0  0000FFFC   41414141   XXXXXX41  1  0         3  2  
   4100  0  0  00000050   00000000   00000000  0  0               1

Synthesis

The CPU core was synthesized for several different FPGAs:

• Xilinx Spartan-3E Starter Kit Board with a XC3S500 used 2021 of 4656 slices (43 percent). Image includes DDR and Ethernet controllers.
• Removing the multiplication unit reduces the size by 558 slices.
• Xilinx Spartan-3 Starter Kit Board with an Xilinx XC3S200 Spartan-3 FPGA.
• Altera EP20K200EFC484-2X FPGA.

Status

• All MIPS I(TM) instructions are implemented and tested (except the unsupported previously patented unaligned load and store opcodes).
• Currently running on an Altera EP20K200EFC484-2X FPGA and a Xilinx XC3S500 and XC3S200 FPGA.
• Also running on a Xilinx Spartan-3E starter kit with DDR SDRAM, Ethernet MAC, and Flash Controller.
• Running at 50 MHz on newer Xilinx FPGAs with three stage pipeline.
• See "opcodes.asm" for regression test.
• Supports Interrupts.
• Includes several C test programs: Calculating PI; Prime Numbers; Showing Numbers Using Words; the Plasma RTOS; and single precision floating point library.

Disclaimer

MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.

Legal Notice

The Plasma CPU project has been placed into the public domain by its original author and is free for commercial and non-commercial use.

This software is provided "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.

Avoiding Limitations

This section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they were patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. [The patent for the unaligned memory access instructions expired Dec 23, 2006.]

Most RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. If needed, there is a GCC patch to never generate unaligned memory accesses at ultra-embedded->GCC Modifications.

The second main limitation of the Plasma CPU is that exceptions (BREAK and SYSCALL opcodes) must not be placed immediately after a branch instruction (in the branch delay slot). The main uses for exceptions are software interrupts for debugger support and calling operating system calls.

Plasma CPU Web Articles

Several groups have published how they have used the Plasma CPU.

• Book: System-level Test and Validation of Hardware/software Systems
• IEEE: Low-Cost Software-Based Self-Testing of RISC Processor Cores
• IEEE: A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA
• IEEE: Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores
• IEEE: Software-Based Self-Testing of Embedded Processors
• IEEE: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
• IEEE: Floating Point Hardware for Embedded Processors in FPGAs
• Research: Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report
• Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level
• Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip
• Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism
• A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in Homogeneous MPSoC systems
• Evaluating the Impact of Task Migration in Multi-Processor Systems-on-Chip
• Exploration of task migration techniques for distributed memory MultiProcessor Systems on Chips
• Thesis: Efficient Verification of Bit-Level Pipelined Machines Using Refinement
• Thesis: Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores
• Spanish: Design, Evaluation and Implementation of a Multicore Processor
• Portuguese: Harvard Architecture?
• Portuguese: Report of the Draft Amendment of the Organization of Interface
• Usage: Plasma soft processor on the Spartan board
• Verilog: Veritak VHDL to Verilog Translator
• Verilog: YF32 - A simple 32-bit CPU SOC Platform [original Chinese]