# Quadrature Oscillator :: Overview

## Project maintainers

## Details

Name: qo

Created: Aug 26, 2009

Updated: Jun 8, 2014

SVN Updated: Jun 8, 2014

SVN: Browse

Latest version: download

Statistics: View

## Other project properties

Category: DSP core

Language: VHDL

Development status: Stable

Additional info:
Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

## Description

This project is a digital signal processing (DSP) implementation of a circuit that provides periodic samples of both sine and cosine waveforms. Technically, it is called a "discrete-time discrete-amplitude binary recursion oscillator." Although that description sounds complex, the operation of the circuit is not complicated. This particular implementation uses a multiplier and an adder, and can be configured to produce sine/cosine output at the desired frequency and with the specified number of bits per sample.

The sine and cosine outputs represent the projections of a rotating vector, or complex phasor if you like, along the real and imaginary axes of a 2-dimensional Cartesian coordinate space. The vector is rotated a fixed amount with each new sample. Is this just as clear as mud?

Well, it does take some multipliers to implement the rotation matrix, but otherwise, it's a fairly quick implementation...

The number of samples per cycle is given as a generic quantity, and the initial values for the vector are zero for sin_o, and +1 for cos_o. The numerical quantities are represented as signed 2's complement numbers, in Q1.(AMPL_BITS-1) notation.

The frequency of the oscillator has been fixed at the lowest possible value. The intention is that by varying the sample rate, sine and cosine waves of different frequencies can be produced. For example, if the system clock is at 50 MHz, and SAMPLES_PER_CYCLE=1000, then it should be possible to create output at 50 kHz by setting the clk_en_i input to '1'. For lower frequencies, just provide a stream of clock enable pulses at the appropriate rate.

This VHDL code has been tested via simulation, and synthesis in actual hardware. The rounding technique used in this module did not keep the output amplitude from decaying, so a once-per-cycle "amplitude reset" is included to ensure that the output is stable over time.