OpenCores

RapidIO IP library :: Overview

Details

Name: rio
Created: Jan 8, 2013
Updated: Mar 21, 2014
SVN Updated: Mar 24, 2014
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: VHDL
Development status: Beta
Additional info: none
WishBone Compliant: No
License: LGPL

Description

This project was founded in 2013 when Bombardier donated some of its RapidIO IP cores that had been developed in an internal project.

It contains a collection of IP cores that can be used to build RapidIO 2.2 capable devices, for example an end point, a switch or a switch with internal endpoints.

Below are brief descriptions of the existing IP cores that are currently available and some that will be available in a near future.

VHDL

RioSwitch.vhd
This IP core implements RapidIO packet switching between a configurable number of ports. It can receive and process maintenance packets to do basic switch configuration.
Has been synthesized for Spartan-6.
Status: Available

RioPacketBuffer.vhd
This IP core implements a RapidIO packet queue. It can store a configurable number of packets in a configurable sized memory.
Has been synthesized for Spartan-6 and Virtex-6.
Status: Available.

RioSerial.vhd
This IP core implements RapidIO LP-serial Physical Specification, but only the transmission channel independent protcol parts. It needs a PCS layer that maps the RapidIO symbols to a physical hardware to work. This allows to develop different PCS layers for different FPGA architectures. For example Altera and Xilinx has different tranceiver blocks to support the high speeds of RapidIO but this way the same protocol parts can be used. This also allows the development of custom PCS layers that does not follow the standard and that can use existing legacy communication infrastructures (for example parallell buses, SPI, ethernet, UART, etc.).
Has been synthesized for Spartan-6 and Virtex-6.
Status: Available.

RioWbBridge.vhd
This IP core implements a bridge between a RapidIO network and a Wishbone bus. It acts as a RapidIO slave endpoint and accepts NWRITE and NREAD packets that are converted into Wishbone accesses. It can be attached to a RioPacketBuffer IP module which in turn is connected either interfacing a RioSwitch (switch with local end point) or interfacing RioSerial (stand alone end point).
Has been synthesized for Spartan-6 and Virtex-6.
Status: Available.

srio_pcs_struct.vhd
This IP core implements a PCS (Physical Coding Sublayer) that uses a Virtex-6 GTX-Quad (4-Lane FPGA SerDes) in order to create support for 1x/4x, 3.125Gbps per lane operation.
Has been synthesized for Virtex-6.
Status: Available. Basically works, but poorly tested.

RioPcsUart.vhd
This IP core implements a PCS (Physical Coding Sublayer) that uses an 8-bit UART as its transmission channel. It can be used by the RioSerial IP module to send RapidIO packets over a standard 8-bit, no parity, 1 stop bit, UART. It has some similarities to PPP.
Has been synthesized for Spartan-6.
Status: Available.

EthSwitch.vhd
This IP core implements a simple self-learning Ethernet switch that works either stand-alone or that can be plugged into a RapidIO switch and work in parallell with it. It makes it possible to build hybrid Ethernet-RapidIO switches.
Status: Under development, will be available late 2014.

C-code

riostack.c
This C-code contains an implementation of RapidIO LP-serial Physical Specification, but only the transmission independent protocol parts. The C-code is written without using any OS-libraries and can be integrated into any microcontroller. It requires a custom symbol codec between the transmission channel and the lower parts of the C-stack implementation. It also requires an upper-half to interface a user application or an operating system.
It has been successfully integrated into a Linux device driver and a small micro controller running FreeRTOS.
It has two compiling options, non-transparent and transparent. The non-transparent answers received maintenance request packets automatically and is inteded for a normal end point implementation. If the transparent option is used, all maintenance requests are passed to upper parts of the stack. This makes it possible to, for example, simulate a switch or to emulate a full RapidIO network in software.
Status: Available.

riocodecuart.c
This C-code contains an implementation of a symbol codec that can handle a data stream generated by the IP core RioPcsUart. It is provided as an example and needs to be integrated into a custom codec suitable for the target processor.
Status: Available.

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