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Generic AXI interconnect fabric

## Description

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from [http://www.provartec.com](http://www.provartec.com)edatools

## Related projects

Generic AXI master stub  
[http://opencores.org](http://opencores.org)project,axi\_master  
  
Generic AXI slave stub  
[http://opencores.org](http://opencores.org)project,axi\_slave


<h2 id="description">Description</h2>
<p>Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from <a href="http://www.provartec.com" target="_blank">http://www.provartec.com</a>edatools</p>
<h2 id="related-projects">Related projects</h2>
<p>Generic AXI master stub <br />
<a href="http://opencores.org" target="_blank">http://opencores.org</a>project,axi_master <br />
<br />
Generic AXI slave stub <br />
<a href="http://opencores.org" target="_blank">http://opencores.org</a>project,axi_slave</p>


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Generic AXI interconnect fabric

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