OpenCores

RTF65002 :: Overview

Project maintainers

Details

Name: rtf65002
Created: Sep 5, 2013
Updated: May 4, 2014
SVN Updated: May 4, 2014
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

The RTF65002 is a 32 bit processor with an instruction set influenced by the 6502 instruction set. It is a 16 register 32 bit word oriented design. The RTF65002 includes 65C816/65C02 emulation modes allowing it to run existing code. In native 32 bit mode the opcodes are redefined in a fashion suitable for 32 bit mode. An attempt has been made to follow the same pattern as the 6502 for opcodes. For instance opcode 69h is an add instruction on the 6502; it's an add instruction on the RTF65002 as well.

Features

- 32 bit WISHBONE burst mode compatible bus interface
- independant instruction and data caches
- variable length instructions; from one to seven bytes
- 16 entry 32 bit general purpose register file, plus independant stack pointer
- 65C02 and 65C816 emulation modes
- non-overlapped pipeline; minimum CPI is 2

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.