Simple Asynchronous Serial Controller :: Overview
Project maintainers
Details
Name: sasc
Created: Sep 17, 2002
Updated: Mar 30, 2006
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language: Verilog
Development status: Stable
Additional info:
FPGA proven
WishBone Compliant: No
License:
Description
Simple asynchronous serial controller (aka UART). Includes 4
byte receive and a 4 byte transmit FIFO (FIFO size can be easily
adjusted). External baud rate generator (included). Very small.
Features
- Implemented in Verilog
- Flow Control (CTS/RTS)
- 1 start bit, 1 stop bit, NO parity
- 4 byte receive FIFO
- 4 byte transmit FIFO
- Fully Synthesisable
- 102 LUTs in a Spartan II