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SystemC to Verilog Synthesizable Subset Translator :: Overview

Details

Name: sc2v
Created: Oct 8, 2004
Updated: Nov 30, 2015
SVN Updated: Nov 30, 2015
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language:
Development status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License:

Features

- Full source code
- PDF documentation
- Written using lex and yacc tools

Description

The sc2v translator is a software tool that translates a SystemC RT description into a Verilog equivalent one.
The sc2v translator is based on lex and yacc tools.
You need lex and yacc installed in order to compile sc2v.


This work is given by Universidad Rey Juan Carlos (Spain)
www.gdhwsw.urjc.es

Status

- Version 0.5
- TODO: See README File

- LOOKING FOR CONTRIBUTORS

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