|Feb 14, 2012
||SDRAM Controller Actel FPGA bench Mark result are added
|Feb 2, 2012
||Frequently asked Question and Answer Section is added
|Jan 30, 2012
||Application Interface is Wish Bone compatible
|Jan 24, 2012
||Design and Verification changes are done to support 8 Bit SDRAM. Now controller support 8/16/32 Bit SDRAM memory.
|Jan 22, 2012
||SDRAM Controller with 16/32 Bit Basic design is completed with automated testbench
|Jan 18, 2012
||16/32 Bit SDRAM Controller verilog RTL with Automated Test bench are uploaded into SVN under sdr_ctl project. Interested user are welcome to validate the IP.
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