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Features & Arch

- SpW Interface
- A Pure synchronous design(more reliable,works well in fpga) written in verilog 2001, completely open
- Annother high speed design(preparing) with low frequency FPGA(or other hosts) system clock between 20-150
- Router
- 16x2 symmetrical SpW interface.
- 16x16 buffered switch matrix

- Offer ISE style alterable testbench *.tf that also could be *.v
- Use some OC IPs such as eth_fifo, synchronizer_flop,with WISHBONE slave interface and WISHBONE memory interface.
- Triple Modulo Redundant (TMR)

The architecture of SpW has two indepedent top modules: 1) the SpW node interface for SoC or just standard IC includes CODECs, WISHBONE slave interface(the "SpW HOCI", HOst Control Interface) and WISHBONE memory interface(the "SpW COMI", COmmunication Memory Interface) ; 2) the SpW Router to form SpW network.
So all things refered below have these two branches.

[SpaceWire]
....|
....+--SpW Interface(I/F)--+
....|................................+--CODEC--+
....|................................|................+- Tx
....|................................|................+- Rx
....|................................|................+- PPU
....|................................+-- FIFO
....|................................|
....|................................+-WB interface-+
....|................................|....................+- COMI
....|................................|....................+- HOCI
....|................................+-JTAG inout
....+--- SWR ---+
......................+- SpW Ports (CODEC+FIFO)
......................+- Routing Matrix -+
......................|........................+- eth_fifo(as buffer cell)
......................|........................+- CSer
......................|........................+- LSer
......................+- Control & GPIO
......................+- Tick Counter

Status & limits

Draft done: CODEC and the SpW interface with WISHBONE interface, buffered switch matrix.
Now i am writing a second CODEC for high speed. All the problem is clock. (But the Rocket IO of Xilinx Virtex Pro may be helpfull.)

The pjt is so rough now. Anyone who has interest in developing this pjt together, or need(or exchange) more informations, please contact me :
btltz@opencores.org or
btltz@mail.china.com


TODO: - The high speed interface is in developing
- The Router and interface to other industrial standard buses
- Post-translate simulation prove

- Core Func Limitations:
- could not support high speed now

- Conformity Limitations:
- Link Interfaces
- The synchronous receiver use a global clock instead of using "XOR"ed rx clock.
-
- Router
- Group adaptive routing now rely on "routing table" not "configuration register"(see subclause 10.2.9.6 of ESCC-E-50-12A)
- Because buffered switch matrix is adopted, though use whormhole routing, no output ports "busy" marker to the scheduler but the "full" flag of a particular cell(FIFO)

Specification

- Diff & Relation with IEE1355 device(eg. Atmel.Inc "TSS901E" which also called "SMCS332")
The SMCS devices implement is based on IEEE1355. Due to the current version of SpaceWire was intend to come as "IEEE1355.2", there's some change from IEEE1355.
- Not like the Atmel's "TSS901E"(or called "SMCS332"), this ip core dosen't use a "clk10" but only a global clock "gclk".The "clk10" is not indispensable according to the SpaceWire standard and this may also be convenient.
- Note that not like TSS901E,the node channels doesn't support wormhole routing. All routing function is performed by Routers.

- Now the detailed specifications are not ready, but a readme.txt is available
- I have draw some schemetics in the very preliminary doc, you could check that

IMAGE: SpWinterfacewithCODEC.JPG

FILE: SpWinterfacewithCODEC.JPG
DESCRIPTION: SpW interface with CODEC

Industrial info & note

- Important Notice:
A IP vendor "SpaceWire UK" provids VHDL CODEC and SpaceWire Switch Core (Router) IPs & Design Services for the Space Industry. I am sure i don't want to disturb this new ip vendor and I also had consulted their ip schemes. Our try is just want to contribute to promoting the SpW standard. We also have no relations with that firm.
Their addr is:
http://www.spacewire.co.uk

- 1) A new IP vendor DSI in Germany offers VHDL SpW CODEC (language=German. Their English Webs is preparing --- Observed April 12, 2005).
http://www.dsi-it.de
- 2) 4Links and star-dundee are two important firms in SpaceWire technology.
STAR-Dundee Ltd is from the Space Systems Research Group of the University of Dundee in Scotland.
http://www.4links.co.uk/
http://www.star-dundee.com/

- 3) For detailed industrial info, please reference the readme.txt file.

- 4) Xilinx has developed a crossbar switch demo(in 2004). They offer a application document and a bit file(demo) for Virtex II and Virtex II Pro device if you register on Xilinx Web.

- 5) Yahoo! 's group of SpaceWire may be very interest for someone who has deep interest.
http://groups.yahoo.com/group/spacewire/messages

IMAGE: Router.JPG

FILE: Router.JPG
DESCRIPTION: Router Scheme

Description

SpaceWire (SpW) grown organically from the needs of on-board processing applications. It's a network of spacecraft/aerocraft with Routers.

Instead of customization in builting system on a project-by-project basis resulting in long development at high cost and risk, SpaceWire focused on the definition of an network architecture for payload data systems. Processing units, mass-memory units and down-link telemetry systems developed for one mission can be readily used on another mission, reducing the cost of development, improving reliability.
(SpaceWire is currently being installed on several NASA and European Space Agency (ESA) spaceships to support onboard communications during space missions.
---27 January, 2003)

SpaceWire standard has taken into consideration two existing standards, IEEE 1355-1995 and ANSI/TIA/EIA-644.

For official publication, please visit
http://www.estec.esa.nl/tech/spacewire
to download ECSS-E-50-12A "SpaceWire - Links, nodes, routers and networks" by ESTEC, ESA(European Space Agency).

For IEEE1355, you could visit
http://grouper.ieee.org/groups/1355/ or http://www.1355.org
"IEEE 1355-1995 Heterogeneous InterConnect (Low cost, low latency, scalable serial interconnect for parallel system construction)."