OpenCores

OpenSPARC-based SoC :: Overview

Details

Name: sparc64soc
Created: Mar 30, 2010
Updated: Oct 13, 2011
SVN Updated: Oct 8, 2010
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info: none
WishBone Compliant: No
License: GPL

Status

Project is alive of 17th May 2010. Please try, find bugs, report and develop. We have enormous amount of TODO (see the bugtracker) so each developer is welcome.

Description

OpenSPARC-based SoC is a project aimed to create a SoC based on OpenSPARC cores (T1 and T2) with OpenCores and other open-source peripherals added, and having Linux/OpenSolaris running on it.

Achievements

Main success now is a OS2WB module that bridges the T1 core and FPU to Whishbone bus. With the other obvious components (DRAM, flash, UART) it is able to boot Ubuntu Linux 2.6.22 normally and 2.6.30 core in rescue mode.
The integer register file (IRF) was redesigned for FPGA, so the four-thread T1 core was shrunk by 25% of logic and 15% of registers. Now it will be possible to build double core system on the Stratix-IV board with small changes in OS2WB.
There is also a whole project source for the Altera StratixIV kit, you will just need to generate standard memories, PLL and DDR3 controller. Documentation will be added soon, meanwhile do not hesitate to ask.

Nearest aims

As a first step, we will build the single-core OpenSPARC T1-based SoC including:
- full or reduced OpenSPARC T1 CPU core
- OpenSPARC FPU
- bridge to connect the CPU and FPU to the Whisbone bus
- Nor flash controller
- UART
- OpenCores Ethernet controller
- bridges from Whishbone to Altera and Xilinx DRAM controllers

Now operating system is Linux 2.6.22 (Ubuntu), we have compiled the 2.6.30 core to support the Ethernet, it is able to boot in rescue mode already. We have cross-toolchain and working on the x86 machines.

Developers wanted - contact maintainers.

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