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synchronous_reset_fifo with testbench :: Overview

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Details

Name: synchronous_reset_fifo
Created: Oct 9, 2011
Updated: Dec 19, 2011
SVN Updated: Dec 19, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Memory core
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL

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