OpenCores

TotalCPU :: Overview

Project maintainers

Details

Name: totalcpu
Created: Jun 8, 2007
Updated: Jun 16, 2007
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License:

Description

TotalCPU is RISC core with 12-bit instruction width and variable data width (from 12 to 64 bits). It is completely realized on Verilog-2001 and has two variants of implementation - with program counter placed in register block or defined as a standalone register. The first variant requires less hardware resources but it is almost 2 times slower then the second variant. It has its own instruction set that doesn’t depend upon data path width.

the description and sources of TotalCPU are http://www.opencores.org/cvsweb.shtml/totalcpu/ (here)

Status

- Design done

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.