UART 16550 core

Project maintainers

Details

Name: uart16550
Created: Sep 25, 2001
Updated: Mar 9, 2018
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 14 reported / 1 solved

Star18you like it: star it!

Other project properties

Category:Communication controller
Language:
Development status:Stable
Additional info:
WishBone compliant: Yes
WishBone version: n/a
License:

Description

uart16550 is a 16550 compatible (mostly) UART core.

The bus interface is WISHBONE SoC bus Rev. B.

Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other.

The datasheet can be downloaded from the CVS tree along with the source code.

Status

Aug 2001
Core updated and some more bugs fixed. It is now being verified more thoroughly but it is mostly usable.
27.05.2001
Documentation and core code are updated.
17.05.2001
The core is finished unless more bugs are found.
The test bench is very basic yet and is asking for your help to expand it. :-)
26.01.2002
The core is functional in polling mode, checked on FPGA.
Should be functional in interrupts mode too but not verified fully in hardware.
Monitor debugging feature is added
All known bugs fixed.
28.01.2002
The core is functional in all modes (interrupt and polling mode), checked on two different boards.
Full operational in uCLinux using included 16550 driver.