USB 1.1 PHY (VHDL)

Jun 4, 2016	Update to the usb_tx_phy.vhdl source corrects the recently reported bit-stuffing issue (USB spec:"If required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (EOP) signal."). This issue caused very rare (but hard to find) problems.	Neumann, Martin
Apr 25, 2013	virified in a FPGA project	Neumann, Martin
Mar 18, 2011	Brief overview added	Neumann, Martin
Mar 18, 2011	Project moved to Communication Controller, was in wrong category (arithmetic core)	Neumann, Martin

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