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USB 1.1 Function IP Core :: Overview

Project maintainers

Details

Name: usb1_funct
Created: Sep 19, 2002
Updated: Jan 27, 2012
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

USB 1.1 slave/device IP core. Default configuration is 6 endpoints:
1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk
Out, 1 Interrupt IN. Includes control engine, providing full enumeration
process in hardware - no external micro-controller necessary.
Derived from my USB 2.0 Function IP core, except all the high speed
support logic has been ripped out and the interface was changed from
shared memory to FIFO based.

A basic test bench is now included as well. It should be viewed
as a starting point to write a more comprehensive and complete
test bench.

I expect the users of this core to have some fundamental USB knowledge
and be familiar with the UTMI specification and with the general USB
transceivers (e.g. from philips). If you are not familiar with these two
you should check out www.usb.org and read up on this subject ...

Features

- USB 1.1 Compliant Function
- Hardware enumeration support
- No micro controller/CPU required
- FIFO based interface
- Written In Verilog
- Fully Synthesisable
- Tested in Hardware

Status

This core is fully functional and completed.
It was verified in hardware in an XESS XCV800 FPGA prototype board.
- Sept. 25 2002
- Added a basic test bench
- Changed Top Level

Dependencies

To use this IP core, you must also download the USB 1.1 PHY , Generic FIFOs and the Generic memories models.



This IP Core is provided by:

www.ASICS.ws - Solutions for your ASIC/FPGA needs -

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