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USB 1.1 PHY :: Overview

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Details

Name: usb_phy
Created: Sep 16, 2002
Updated: Jan 11, 2017
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn't do any error checking in
the RX section (should probably check for bit unstuffing errors).
Otherwise complete and fully functional.

There is currently no test bench available. This core is very simple
and is proven in hardware. I see no point of writing a test bench at
this time.

I expect the users of this core to have some fundamental USB
knowledge and be familiar with the UTMI specification and with the
general USB transceivers (e.g. from philips). If you are not familiar
with these two you should check out www.usb.org and read up on
this subject ...

Features

- FPGA or ASIC implementation possible
- 8 bit wide unidirectional UTMI interface
- serial parallel conversion
- bit stuffing/unstuffing
- NRZI encoding/Decoding
- DPLL
- Implemented in Verilog
- Fully synthesizable (runs well over the required 48MHz in a Spartan II)
- Very small: 111 LUTs (7%) of Spartan II XC2S50

Status

This core is fully functional and completed.
It was verified in hardware in an XESS XVC800 FPGA prototype
board with an USB 1.1 IP core I have written.



This IP Core is provided by:

www.ASICS.ws - Solutions for your ASIC/FPGA needs -

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