OpenCores

configurable cordic core in verilog :: Overview

Project maintainers

Details

Name: verilog_cordic_core
Created: Sep 14, 2008
Updated: Aug 12, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Arithmetic core
Language: Verilog
Development status:
Additional info: Design done, FPGA proven
WishBone Compliant: No
License:

Description

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details. Source and user manual available here

Status

- Tested in hardware

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.