OpenCores

configurable cordic core in verilog

Project maintainers

Details

Name: verilog_cordic_core
Created: Sep 14, 2008
Updated: Nov 9, 2018
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
Star10you like it: star it!

Other project properties

Category:Arithmetic core
Language:Verilog
Development status:
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included manual for details. Source and user manual available here

Status

- Tested in hardware