veristruct :: Overview
Other project properties
Veristruct is an an IEEE1364.1995 preprocessor that adds some C-style struct support to the Verilog language. It takes as input Veristruct files (with a .vs extension) and struct definition files (with a .struct extension). It outputs standard Verilog files (with a .v extension). Veristruct files are, for the most par t, standard Verilog files—but, as well as the normal nets and regs, bundled, hierarchical variables can be declared and used.
Veristruct can process one veristruct file per invocation (which may include many .struct struct definition files).
Veristruct is written in object oriented Perl. Please feel free to fix any bugs you find!
Veristruct outputs IEEE1364.1995 compliant .v files. Structs declarations are expanded into their elements, and struct element references are expanded into formally compliant variable names. Double underscores are used to indicate depth. When entire structs are referenced (instance names are used without element references) a guess is made as to what is desired. In sensitivity lists and module por t lists, the name is exploded into its constituent elements (and appropriate
separator tokens are added). In module instance por t lists, it is assumed that the module being instantiated has multiple ports with the instance name as the base (that will be the case if the module was written in Veristruct).
- Working with certain limitations.
The following limitations currently exist within Veristruct:
- Namespace collisions not detected: Veristruct currently does no checking for namespace collisions. If you don’t use double underscores in your variables names, though, you should be fine.
- Limited lvalue support: Slices of some struct elements (and whole structs, in most contexts) cannot be lvalues. Veristruct will return an error when it encounters these.
- Structs can only be declared in .struct files: This is a deliberate limitation. It avoids polluting the Verilog syntax even more.
- ‘ifdefs ignored: Because Veristruct is not designed to replace the normal Verilog preprocessor, it does not do its job. As such, you will need to ensure that do not rely on your structs being conditionally included using normal pre-processor directives. There are many ways around this. Ranges in structs can be tick defined, and variable declarations can be surrounded in ‘ifdefs, which will get honoured later.