Versatile IO :: Overview
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Details
Name: versatile_io
Created: Mar 31, 2009
Updated: Apr 23, 2009
SVN Updated: Oct 26, 2011
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language: Verilog
Development status: Planning
Additional info:
none
WishBone Compliant: Yes
License: LGPL
Overview
This is a modular IO component. With this modular IP design tou can get multiple (by default up to 8) IO channels. Each channel has a RX and TX FIFO with depth 31 bytes. The FIFO is based on the Versatile FIFO also available from OpenCores. All IO channels have a common bus interface compatible with 16550 UART. This makes software integreation easier
This IP support many different types of IO
- 16550 compatible UART
- LED control
- RGB LED control
- RC5 compatible IR receiver