Viterbi HDL Code Generator
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2009-02-09 10:19 | Verilog_TD-SCDMA_rate=0.5_Viterbi_decoder.rar | a TD-SCDMA version of K=9, rate=1/2 decoder, generate code words is (561 753) in octal description |
| 2009-02-04 13:33 | morpheus1.3release.rar | %Version 1.3 Add Direct Traceback Option and Self test module Rejust the GUI Interface. |
| 2009-01-20 04:24 | k=9_rate=0.5_VHDL.rar | A VHDL version for K=9, Rate = 1/2, code= (431, 285) convolutional code It's a viterbi decoder written in VHDL, in the requirement of Mitchell. Add vhcg_pkg.vhd |
| 2008-12-20 15:46 | morpheus1.2release.rar | 1.2 release adjust directory structure, new testbench and scripts all in this package. |
| 2006-04-26 20:54 | morpheus1.1release.rar | 1.1 release add synchronouse RAM support improve the interface |
| 2005-07-12 06:39 | Specification.pdf | description |
| 2004-10-25 13:00 | morpheus.tar.gz | tarball file include everything. add acs2.mod. |
| Description | Link-tag | Download | Date |
| It's a zip file, rename to .zip( | Show | Link | 2010-02-01 06:02 |
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