PDP-11/70 CPU core and SoC :: Overview

Overview

Features

Implementation

Installation

Verification

Systems

Performance

Roadmap

Resources

Thanks

News

Downloads

Bugtracker

Description

The project contains a complete PDP-11 system: a 11/70 CPU with memory management unit, but without floating point unit, a basic set of UNIBUS peripherals (DL11, LP11, PC11, RK11/RK05), and last but not least a cache and memory controllers for SRAM and PSRAM. The design is FPGA proven, runs currently on Digilent S3BOARD , Nexys2 and Nexys3 boards and boots 5th Edition UNIX and 2.11BSD UNIX.

This is a retrocomputing project, rebuilding hardware and running software from the late 70s and early 80s. To get into the tune see Figure D-1, a 11/70 console, and Figure F-2, a baseline system setup.

News 2013-05-12:: Release w11a_V0.58 available for details see section Releases.

For more details see the sections:

• Features
• Implementation
• Installation
• Verification
• Systems
• Performance
• Roadmap
• Resources
• Thanks

Status

Running Systems

The project holds all the sources to synthesize a complete system. Complete configurations for three boards are currently part of the project, the Digilent S3BOARD, Nexys2 and Nexys3 boards. See section Features: Complete Systems for details.

So far two UNIX systems have been successfully booted on the w11a:

• UNIX 5th edition
• 2.11 BSD UNIX

See section Systems for details, including links to the disk sets.

Known Issues

There are some known difference between w11a and 11/70 and also known bugs in the current w11a implementation (see w11a_known_issues.txt). They affect the behaviour in cases like fatal stack errors or certain double faults which don't occur in the normal operation of an operating system, and if they happen, in general lead to a crash anyway.

The known differences are not considered worth fixing them, while the known bugs will be addressed in future versions of the w11a core.

The current implementation of the backend server process is an over the years grown big monolithic perl script, neither maintainable or well performing. It is ok for 'proof-of-principle' demos, but not for any real work on the systems. It will be replaced in the next revision.

Given that the w11a boots 2.11BSD the cores are considered 'Design Done' and 'FPGA proven', given the other loose ends listed above the project is still considered 'Alpha' quality.

Milestones

Being a 'leisture time project' things evolve at a modest pace. Key milestone so far were:

•	Apr-2013:		new C++/Tcl backend server, w11a designs operate with rlink over USB
•	Jan-2012:		Cypress FX2 USB controller support added, rlink and config over USB.
•	Dec-2011:		Spartan-6 port of w11a added (for Digilent Nexys3 board).
•	Jul-2010:		OpenCores project w11 created; w11a V0.5 tagged and released.
•	May-2010:		w11a systems ported to Digilent Nexys2 board; lots of cleanup.
•	Sep-2009:		2.11BSD UNIX boots to multi-user mode on w11a on FPGA.
•	Aug-2009:		UNIX 5th Edition boots on w11a on FPGA.
•	Jun-2009:		Found 11/70MP system manual on bitsavers. Most of IIST implemented. Too early, but fun.
•	Dec-2008:		Finished the last of three 2.11BSD patches, now 2.11BSD boots of a RK05 disk set and runs on a 11/70 without FPP in simh.
•	Mar-2008:		Full system with CPU, cache, and minimal I/O system runs on FPGA.
•	Sep-2007:		rri (rbus+rlink) implemented, w11a runs on FPGA (Digilent S3BOARD).
•	Sep-2006:		CPU and MMU implemented, simple test codes run.
•	Jun-2006:		Re-discovered a pile of PDP-11 manuals in a forgotten box full of old paper work. This triggered the idea, and with simh, ghdl and bitsavers at hand, 2.11BSD as target OS and a 11/74 picture as desktop background it quickly became a project.

Releases

Major releases are tagged on svn, minor releases are denoted only via the svn revision.

Release	Date	svn tag	svn rev	README		Comment
w11a_V0.58	2013-05-12	-	21	README		LP11,PC11 support added; old backend retired; operating system kits re-organized
w11a_V0.57	2013-04-27	-	20	README		w11a systems with rlink over USB on nexsy2 and nexsy3 boards
w11a_V0.562	2013-04-13	-	19	README		Phase 2 of new C++/Tcl backend, add cpu and first device support; add asm-11 assembler
w11a_V0.561	2013-01-06	-	18	README		Add bugfixes, Cypress FX2 simulation model, and test designs for Nexys3 and Atlys boards
w11a_V0.56	2013-01-02	-	17	README		Add Cypress FX2 USB interface controller; FX2 firmware supporting jtag access and data transfer; test system for rlink over USB verification
w11a_V0.55	2011-12-23	-	16	README		Add xon/xoff (software flow control) support to serport library; Add test design for serport verification
w11a_V0.54	2011-12-04	-	15	README		Add Nexys3 port of w11a
w11a_V0.532	2011-11-20	-	14	README		Add test design for 'human I/O' interface; migrate to use numeric_std
w11a_V0.531	2011-09-12	-	12	README		Prepare upcoming support for Spartan-6 (nexys3 and atlys) and Cypress FX2 USB (nexys2/3 and atlys)
w11a_V0.53	2011-04-17	-	11	README		Introduced new backend written in C++ and Tcl. Phase 1 with functionality to execute simple test benches
w11a_V0.52	2011-01-02	-	9	README		Introduced rbus protocol V3; reorganize rbus and rlink modules, many renames
w11a_V0.51	2010-11-28	-	8	README		Introduced ibus protocol V2; Nexys2 systems use DCM; sys_w11a_n2 now runs with 58 MHz
w11a_V0.5	2010-07-23	w11a_V0.5	-	README		Initial release: w11a CPU core; basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05; two complete systems for Digilent S3BOARD and Nexys2