PDP-11/70 CPU core and SoC :: Features
Features
Fig F-1: A KB11-C processor without FPP and one Massbus interface, build around 1976 in SN74Sxx Schottky TTL technology. The w11a core has a similar feature set. See also hi-res jpg, and view on backplane in wire wrap technology. Picture courtesy of Dave McGuire, see also Dave's PDP-11/70 site.
Fig F-2: PDP-11/70 Console with 2 RK05 drives with a UNIX 7th edition system (see disk labels in high resolution jpg). The current w11a systems emulate a similar configuration. Picture courtesy of John Holden. See also John's PDP-11 Site.
Fig F-3: w11a running on a Digilent Nexys2 board. The rlink connection is via the RS232 port and a FTDI US232R-100 cable. The mini-USB connector is currently used only to power the board.
The w11a CPU core
The w11a CPU core has a functionality very close to a PDP-11/70 CPU (Model KB11-B or KB11-C) and supports with very few exceptions everything the PDP-11 architecture has to offer:- standard and extended (MUL, DIV, XOR, ASH) instruction set
- special instructions (SPL, MTPD, ect)
- dual register set
- three processor modes: kernel, supervisor, user
- memory management with 18 and 22 bit addressing and separate instruction and data address space
- UNIBUS mapping support (18->22 bit address translation)
The I/O System
Project goal was to create a retro-computing platform able to run the historical UNIX systems and other original software. The I/O system is therefore setup to have the same register model and semantics as the original DEC UNIBUS peripherals. To interface this to contemporary I/O hardware all I/O transactions are emulated by a backend server in the following way:- all device registers are effectively dual-ported, visible from the w11a core via a bus structure named ibus with an addressing model similar to the DEC UNIBUS, and from the backend server via a 'remote register interface', called rri.
- the rri communication between fpga and backend server can be done directly via bus structure named rbus or over any bi-directional byte stream connection via the rlink protocol.
- an attention mechanism allows the efficient detection of significant device register state changes by the server, which will usually read the device state, emulate the desired I/O transaction and update the device state. DMA transfers are emulated by direct memory access over rbus.
- in current 'proof-of-principle' implementation the backend server is a process running on a normal Linux system, the communication is done over an rlink via RS232 or USB FIFO channels. See Figure F-3 for such a setup.
- KW11L: line frequency clock
- DL11: console interface
- LP11: line printer
- PC11: paper tape reader/puncher
- RK11: disk controller with 8 RK05 drives (2.4 MByte capacity each)
- IIST: interprocessor interrupt and sanity timer (operationally not used so far, but was fun to do...)
Complete Systems
The project holds all the sources to synthesize a complete system. The systems are comprised of- w11a processor core
- I/O subsystem
- cache subsystem: 8 kByte, 32 bit cache line, fully associative, write-thru
- memory subsystem interface with PDP-11/70 style control registers
- memory controller: depends on board, currently for SRAM and PSRAM
- rlink interface: used as control and debug interface as well as for I/O emulation
Name Board FPGA Clock #flop #luts #slices
[MHz]
sys_w11a_s3 S3BOARD XC3S1000 50 1301 4671 2613(34%)
sys_w11a_n2 Nexys2 XC3S1200E 58 1450 4804 2740(31%)
sys_w11a_n3 Nexys3 XC6SLX16 80 1441 3260 1081(47%)
The Digilent S3BOARD
has 1 MByte SRAM (is61lv2561), the Digilent
NEXYS2
and
NEXYS3
boards have 16 MByte PSRAM (mt45w8mw16b) of which only 4 MByte, the maximum
a PDP-11 can address, are used.
System Configuration
Both systems have the following configuration for the UNIBUS peripherals:
Controller Name CSR VEC PRI Device Names
BSD DEC
IIST MP interrupt/timer 177500 260 6 - -
KW11-L line frequency clock 177546 100 6 - -
RK11 disk controller 177400 220 5 rkxh DKx: (x=0..7)
DL11 console 177560 060 4 cn 0 TT0:
DL11 2nd console 176500 300 4 cn 1 TT1:
PC11 papertape read/punch 177550 070 4 - PP:,PR:
LP11 line printer 177514 200 4 lp 0 LP: