PDP-11/70 CPU core and SoC :: Installation


Download Sources

All sources are contained in the OpenCores svn repository.

Download Pre-Build Bitfiles

Tarballs with ready to use bit files and and all logfiles from the tool chain can be downloaded for releases since w11a_V0.60 from this link. This area is organized in folders for different releases. The tarball file names contain information about release, Xlinix tool, and design

Download OS Kits (disk and tape images)

Tarballs with ready to use operating system image can be downloaded from this link. The tarball file names contain information about OS and media type
See section Systems, the w11a_os_guide.txt, and the README files in the tools/oskit folders for the available OS kits, the procedures to use them, and the license restrictions to obey.


An admittedly still rudimentary documentation can be found in the doc directory, specifically on


A full list of tagged versions and minor releases is given in the 'Change Log' part of README.txt and in section Releases.

Directory Structure

   doc                          Documentation
   rtl                          VHDL sources
   rtl/bplib                    - board and component support libs
   rtl/bplib/atlys                - for Digilent Atlys board
   rtl/bplib/fx2lib               - for Cypress FX2 USB interface controller
   rtl/bplib/issi                 - for ISSI parts
   rtl/bplib/micron               - for Micron parts
   rtl/bplib/basys3               - for Digilent Basys3 board
   rtl/bplib/nexys2               - for Digilent Nexsy2 board
   rtl/bplib/nexys3               - for Digilent Nexsy3 board
   rtl/bplib/nexys4               - for Digilent Nexsy4 board
   rtl/bplib/s3board              - for Digilent S3board
   rtl/ibus                     - ibus devices (UNIBUS peripherals)
   rtl/sys_gen                  - top level designs
   rtl/sys_gen/tst_rlink          - top level designs for an rlink tester
   rtl/sys_gen/tst_rlink_cuff     - top level designs for an rlink over FX2 tester
   rtl/sys_gen/w11a               - top level designs for w11a SoC
   rtl/sys_gen/w11a/basys3          - w11a SoC for Digilent Basys3
   rtl/sys_gen/w11a/nexys2          - w11a SoC for Digilent Nexsy2
   rtl/sys_gen/w11a/nexys3          - w11a SoC for Digilent Nexsy3
   rtl/sys_gen/w11a/nexys4          - w11a SoC for Digilent Nexsy4
   rtl/sys_gen/w11a/s3board         - w11a SoC for Digilent S3board
   rtl/vlib                     - VHDL component libs
   rtl/vlib/comlib                - communication
   rtl/vlib/genlib                - general
   rtl/vlib/memlib                - memory
   rtl/vlib/rbus                  - remote-register-interface - rbus 
   rtl/vlib/rlink                 - remote-register-interface - rlink
   rtl/vlib/serport               - serial port (UART)
   rtl/vlib/simlib                - simulation helper lib
   rtl/vlib/xlib                  - Xilinx specific components
   rtl/w11a                     - w11a core
   tools                        helper programs
   tools/asm-11                 - pdp-11 assembler code
   tools/bin                    - scripts and binaries
   tools/dox                    - Doxygen documentation configuration
   tools/make                   - make includes
   tools/fx2                    - Firmware for Cypress FX2 USB Interface
   tools/fx2/bin                  - pre-build firmware images in .ihx format
   tools/fx2/src                  - C and asm sources
   tools/fx2/sys                  - udev rules for USB on fpga eval boards
   tools/oskit                  - setup files for Operation System kits
   tools/src                    - C++ sources
   tools/src/librlink             - basic rlink interface
   tools/src/librlinktpp          - C++ to tcl binding for rlink interface
   tools/src/librtcltools         - support classes to implement Tcl bindings
   tools/src/librtools            - general support classes and methods
   tools/src/librutiltpp          - Tcl support commands implemented in C++
   tools/src/librw11              - w11 over rlink interface
   tools/src/librwxxtpp           - C++ to tcl binding for w11 over rlink iface
   tools/tbench                 - w11 CPU test bench
   tools/tcl                    - Tcl scripts
Some conventions used throughout the project:
  • test benches are in sub-directories '/tb' under the respective source directory
  • synthesizable VHDL code uses the architecture name syn while code only used in simulation uses the architecture name sim
  • the svn 'Id:' headers in the sources reflect the revision in the svn repository of the author and not the svn revision number of the file in the OpenCores repository.

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