Resources
Original Documentation
For all without a good private library of original manuals the
bitsavers.org document archive of
historical DEC manuals
comes to the rescue. Another good source of original manuals was the
UQ Museum of IT, they are marked with a
(UQ).
{Note November 2010: the UQ site was closed by the University. The URL's
point to the last saved state from
web.archive.org.}.
But be aware that all manuals are
under the
copyright of
DEC,
now held by
HP.
The key documents are:
- General Handbooks
- PDP-11/70 Processor (KB11-C and FP11-C)
- PDP-11/45 Processor (KB11-A, KT11-C, and FP11-B)
The 11/45 is essentially a 11/70 without cache, massbus
and 22 bit addressing, but otherwise very similar.
- J11 Processor
The J11 is an ASIC implementation of a
11/70 with a small number of added and a some removed features.
- Peripherals
Papers
Four papers by
Gordon Bell
nicely cover the PDP-11 from inception to retrospective
(available from
Gordon's website):
Patents
All
patents covering the PDP-11 architecture are
expired
by now. The PDP-11 is completely unencumbered from an intellectual property
point of view since 1995. But it's quite interesting to look through the
patents. They are now easily accessible via
Google Patents.
The key PDP-11 architecture patents are:
- US-Pat 3614740
(1971) - covers PDP-11 Instruction Set (control transfer)
- US-Pat 3614741
(1971) - covers PDP-11 Instruction Set (PC as general register)
- US-Pat 3710324
(1973) - covers 'processor and peripheral connected via single bus'
UNIBUS architecture
Other PDP-11 and UNIBUS related patents are:
Design patents
covered the visual appearance (uspto term:
ornamental design)
of the PDP-11 systems and peripherals, for example
The
trademarks
PDP,
UNIBUS,
MASSBUS,
DEC, and
DIGITAL
(
d|i|g|i|t|a|l
) are all marked as
dead
and are thus expired, the last one in April 2010.
Other PDP-11 FPGA Implementations
Currently there are two other openly available FPGA implementations
of the PDP-11 architecture:
-
Naohiko Shimizu's POP-11: a PDP-11/40 with MMU and EIS,
boots
UNIX 6th edition
from an IDE disk. Written in
SFL.
The POP-11 sources are open source, the SFL-to-Verilog converter
unfortunately not.
See also a
proceedings paper on POP-11 submitted for the Asia and South Pacific
Design Automation 2004 conference.
Naohiko's motivation is to 'Reincarnate Historic Systems on FPGA with
Novel Design Methodology' and use this in teaching, see his presentation
given on the
ICCD 2009
(
abstract,
slides and
proceedings).
-
Brad Parker's FPGA PDP-11: currently a PDP-11/34 but soon a
11/44, boots RT-11,
RSTS V4
and 2.9 BSD from an IDE disk via an RK11 emulation.
Written in Verilog. This project evolved independantly of the w11
on an essentially parallel time scale. See also
SD Times Article.
