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Wishbone LPC Host and Peripheral Bridge :: Overview

Project maintainers

Details

Name: wb_lpc
Created: Mar 1, 2008
Updated: Jan 31, 2012
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Description

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.

None of this has been tested (yet) with a third-party LPC Peripheral or Host.

Features

- Compliant to Intel(r) Low Pin Count (LPC) Interface Specification Revision 1.1
- Wishbone Slave to LPC Host Module
- Memory Read and Write (1-byte)
- I/O Read and Write (1-byte)
- Firmware Memory Read and Write (1-, 2- and 4-byte)
- DMA support
- Wishbone Master to LPC Peripheral Module
- Memory Read and Write (1-byte)
- I/O Read and Write (1-byte)
- Firmware Memory Read and Write (1-, 2- and 4-byte)
- DMA support
- Serial IRQ Host and Slave Controllers
- Supports "Serialized IRQ Support for PCI Systems" Rev 6.0 Specification.
- Continuous and Quiet modes.
- 32 interrupts supported.
- Test bench and project file for Xilinx ISE 10.1 included.
- Example applications (Uses the Enterpoint Raggedstone1 PCI Card) http://enterpoint.co.uk/moelbryn/raggedstone1.html
- PCI to LPC Host Controller, with Interrupt support (uses pci32tlite core on OpenCores)
- LPC to 7-segment display.
- Fully static synchronous design with one clock domain
- Technology independent Verilog
- Fully synthesizable

Status

- Tested in simulation
- Tested in Spartan3 FPGA
- LPC Host has only tested with LPC Peripheral bridge, not with actual LPC devices.
- 2008-07-22: Fixed bug: Spec violation for multi-byte firmware accesses
- Tested with LPC eVC written by Daniel Preda, which found all of the bugs in Tracker: http://www.opencores.org/people.cgi/info/danielpreda

References

- Intel LPC Bus Specificaton, Revision 1.1: http://www.intel.com/design/chipsets/industry/lpc.htm
- Serialized IRQ Support for PCI Systems, Revision 6.0: http://dublintrees.com/download/serirq60.pdf
- Implementing Industry Standard Architecture (ISA) with Intel(r) Express Chipsets (White Paper): http://www.intel.com/assets/pdf/whitepaper/318244.pdf
- LPC Bus Information from Wikipedia: http://en.wikipedia.org/wiki/Low_Pin_Count
- Raggedstone1 Spartan3 PCI Card details: http://enterpoint.co.uk/moelbryn/raggedstone1.html

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