Herveille, Richard

DragonBall/68K Wishbone interface

## Description

This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.

## Features

\- 16bit Motorola DragonBall/68K Interface  
\- 16bit full featured RevB.3 Wishbone Classic Master interface  
\- programmable address-bus size  
\- static synchronous design  
\- fully synthesisable  
\- 6LUTs in a Spartan-II, 32LCELLs in an ACEX

## Status

Design is finished and available in Verilog for download from OpenCores CVS.


<h2 id="description">Description</h2>
<p>This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.</p>
<h2 id="features">Features</h2>
<p>- 16bit Motorola DragonBall/68K Interface<br />
- 16bit full featured RevB.3 Wishbone Classic Master interface<br />
- programmable address-bus size<br />
- static synchronous design<br />
- fully synthesisable<br />
- 6LUTs in a Spartan-II, 32LCELLs in an ACEX</p>
<h2 id="status">Status</h2>
<p>Design is finished and available in Verilog for download from OpenCores CVS.</p>


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DragonBall/68K Wishbone interface

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