Asynchronous WISHBONE-compatible SDRAM controller :: Overview
Project maintainers
Details
Name: yadmc
Created: Aug 1, 2008
Updated: Aug 7, 2010
SVN Updated: Aug 7, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Memory core
Language: Verilog
Development status: Stable
Additional info:
none
WishBone Compliant: No
License: GPL
Description
SUPERSEDED BY HPDMC.
Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the Milkymist-devel mailing list.