a VHDL 8254 Timer

syncronisation #3

Closed tkrawuts opened this issue about 13 years ago

I saw syncronisation problems with async clocks: Slow timer input clock(clk) and fast wishbone clock (clk_i), generics set properly.

JKFF U3 in gh_counter_control.vhd has iout and iload on inputs J and K: iout is derived from clk iload is derived from clk_i (ld_msb,dwr )

U3 is clocked with slow clock "clk" and does not see short iload pulses (clk_i) and m0_outh is not cleared so that in Mode 0 the output is not set to 0 when starting a new count by writing lsb/msb.

Below the fix. I don't know if it breaks other modes, but as m0_outh is exclusively for Mode 0 I do not assume so. The fix is not elegant because it still does not synchronize right, it just syncs to the faster clock. Setup/Hold Time issues are still possible.

--- gh_counter_control.vhd 2008-08-02 19:22:28.000000000 +0200 +++ ../../../../modelsim/src/gh_counter_control.vhd 2011-05-13 14:52:06.689707400 +0200 @@ -326,7 +326,7 @@

U3 : gh_jkff PORT MAP (

```
          clk => clk,
```

          clk => clk_i,
          rst => rst,
          j => iout,
          k => iload,

Regards Tobias

hlefevre was assigned about 13 years ago

Yes, there is a problem - but, rather than change the clock on U3, I think the K input should be changed to "load" which is synced with "clk"

On the download page, I added a PDF of the modified file (simple uploads are only possible for documentation now days) there are two modifications in the file, on line 250 and 333 - both changing "iload" to "load"

hlefevre closed this about 13 years ago

Assignee

hlefevre

Labels

Bug

Browse

a VHDL 8254 Timer