aoR3000

Modelsim Altera 10.0d compiles RTL files with errors like "undefined variable" and "already declared". For example: "memory_data_tlb_micro.v(79): Undefined variable: plru."

Well, I confirm this behaviour of Modelsim.

To fix these errors you have to declare the signals / registers before you use them.

I don't really use Modelsim to simulate the design. Verilator doesn't have these kind of problems.

Best regards, Aleksander Osman.