I know very little about Verilog (I do know VHDL) and have run across the following warnings from Altera Quartus II V8.1:
Warning (10236): Verilog HDL Implicit Net warning at can_top.v(589): created implicit net for "rx_inter"
+---------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +----------------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +----------------------------------------------+----------------------------------------+
; can_bsp:i_can_bsp|overload_request_cnt0..1 ; Lost fanout ; ; can_bsp:i_can_bsp|overload_frame_blocked ; Stuck at GND due to stuck port data_in ;
; can_btl:i_can_btl|delay3 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 4 ; ; +----------------------------------------------+----------------------------------------+
The first warning about the implicit net can be "fixed" by adding a wire declaration for the indicated net. However, the warnings about register removal causes me considerable concern. If they are declared I assume they are needed so why are the tools removing them? Has anyone else run into this issue? Is there a bug in the design or a problem with the Verilog code?
Thanks for your help;
Brent Zajac
Found the source of my confusion: for those who wish to know, the signal "overload_request" is hardcoded to a logic 0.