library IEEE; use IEEE.STD_LOGIC_1164.all;
package imdct_package is type type_dct is array (17 downto 0) of std_logic_vector(31 downto 0); end;
package body imdct_package is end;
I am Liu Sixiong ,i want this file: imdct_package.vhd . can you sent it to me.
With the code, I created a VHDL module and it worked... there is not problem ... It was probed on Project Navigator Xilinx IseWebPack v11.1
I do not know how could I Fix this bug. thank you. davs@live.de