Adjustable Frequency Divider

Another glitchy non functional clock divider, ARGH! Atleast in iverilog it shows to glitch when i run an upcounter with posedge inclk that sets a value, and i run a "getter" on posedge in another seq block that is run by the divided by 2 clock.

reg [3:0] set = 0, get;

always @(posedge in_clk) set <= set + 1;
always @(posedge divBy2_clk) get <= set;

Well, when set clocks in from 2 to 3 then, get also clocks in to 3, and not 2 as it should!

SIGH, i'm fucking pulling my hairs out here, been at i for weeks now, lots of failed clock divs of my own, then i tried yours, and it's the same...

:(

reg 3:0 set = 0, get;

always @(posedge clk) set <= set + 1;
always @(posedge q) get <= set;

And this fucking website doesn't work either, i tried to paste code and the parser doesn't web escape the characters, so that the code block's plus and minus chars, etc, disapears.