Hello. I am FPGA, VHDL newby. I try implement this controller on the Xilinx Spartan S3E-250 chip. The number of RAMB16s is 87 out of 12 725% (OVERMAPPED). Please help me. How to use small picture to prevent ram overmapping?
You nee to regenerate the imagegen_bram* netlists to use less BRAM (via coregen) and you need to decrease the size of the image that you want to store (and generate new COE files).
I try bmpParse on smiley bmp file and recive error:
./bmpParse smiley_30x32.bmp smiley_R.coe smiley_G.coe smiley_B.coe smiley.hdr 0 2 File is compressed! The parser did not return a valid reference address for the bitmap data! Exiting...
What's wrong?