MD5 Pipelined
A pipeline has a register between each block so that you can increase the clock speed, because of shorter logical paths between them. In this case it is one block with very long paths not a pipeline.
(I tried to write a MD5 pipeline it doesn't fit on my FPGA(Spartan6 LX9) because the huge amount of D-Type FlipFlops)
You are misinterpreting the design. First, there is a register for every stage in the pipeline. See here:
Note that those are nonbocking assignments that are executed in parallel rather than blocking, which may be a source of your confusion.
Second, just because the code is organized in one large physical block does not mean the design is logically a single block. It is not. Run TimeQuest analyzer and look at the paths, they are actually quite short. On a DE0-Nano with a 50mhz clock, the design functions correctly when a PLL is used to multiply clock to 100mhz. A similar design that used blocking assignments and actually had long paths and no pipeline failed verification at 1mhz on the same hardware.
Finally, if you still don't believe me, look at this screenshot of ModelSim showing that the first digest is not finished until the 65th tick, at which point the pipeline is full and one digest is completed each clk posedge thereafter:
https://raw.githubusercontent.com/John-Leitch/fpga-md5-cracker/master/Hardware/Md5CoreTest.png
If you'd like to see a complete project that cracks MD5's here's the source: https://github.com/John-Leitch/fpga-md5-cracker/
And here's a video of it: https://www.youtube.com/watch?v=fkkoeAJWTOw